Cadence Design Systems IncCadence's PCIe 6.0 PHY/controller IP in TSMC N3 achieved first-pass PCI-SIG compliance and is now available for SoC design-in.
Cadence announced that its PHY and controller IP for the PCIe 6.0 specification, implemented in TSMC's N3 process, achieved first-pass success at the PCI-SIG compliance workshop in late July, passing all official tests at 64 GT/s and earning a place on PCI-SIG's Integrators List. The complete x8 subsystem solution, which includes both PHY and controller, is now available for SoC providers to design in, demonstrating industry readiness for mass production and de-risking adoption for AI/HPC customers. Cadence's vice president of R&D for high-performance PHY, Marc Loinaz, highlighted the solution's best-in-class performance and low power, while Keysight's Brig Asay and PCI-SIG's Al Yanes praised the milestone. Positron AI has licensed the SerDes IP for its AI inference accelerator chip, citing confidence in the subsystem's silicon-proven design and interoperability testing. The PCIe 6.0 standard addresses growing demand for high-bandwidth connectivity in AI and high-performance computing systems, with expected wide adoption in data centers and AI infrastructure.
Cadence Design Systems IncCadence's PCIe 6.0 PHY/controller IP in TSMC N3 achieved first-pass PCI-SIG compliance and is now available for SoC design-in.
Taiwan Semiconductor Manufacturing Co. Ltd.Cadence's PCIe 6.0 subsystem was implemented in TSMC's N3 process, showcasing the node's readiness.
Keysight Technologies Inc
CTO Realty Growth IncPositron AI licensed Cadence's SerDes IP for its AI inference accelerator chip.