Meta Platforms Inc.Meta co-proposed a next-generation CXL-based AI datacenter architecture that boosts accelerator coordination and cuts latency.

Panmnesia, a fabless semiconductor company, and Meta have jointly proposed a next-generation AI datacenter architecture in which an entire datacenter operates like a single chip, as detailed in an invited Review published in Nature Reviews Electrical Engineering. The architecture uses Compute Express Link (CXL) to minimize latency variability beyond the rack, extending cache coherence from within the rack to the whole datacenter. Key hardware elements include a high-fan-out non-blocking switch, a link acceleration unit, and a fabric controller, with optical links extending reach. Compared to a conventional rack-scale configuration, the number of accelerators a single CPU coordinates rises eightfold from two to sixteen, and the coherence domain grows to as many as 960 accelerators, roughly 13 times the reference platform. Round-trip latency falls from the microsecond range to several hundred nanoseconds, and the unit of replacement after a failure narrows from a whole server to a single device. Panmnesia is the first semiconductor startup worldwide to lead an NREE Review, and the article is the journal's first Review on CXL and AI datacenter architecture. The company has implemented the core components in silicon and is preparing them for commercial supply.
Meta Platforms Inc.Meta co-proposed a next-generation CXL-based AI datacenter architecture that boosts accelerator coordination and cuts latency.
Panmnesia led the proposed CXL datacenter architecture, implemented core components in silicon, and is preparing commercial supply.