Synopsys and TSMC Expand AI Chip Design Partnership Across A14, Agentic AI and Advanced Packaging

โดย PR Newswire·TWUS·Read original
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Synopsys announced new collaborations with TSMC spanning A14 design enablement, AI-assisted engineering workflows, CoWoS support for multi-die designs, and unified multiphysics signoff. The companies said Synopsys has achieved A14 certification across digital and analog flows and enabled agentic AI capabilities, giving customers a methodology spanning implementation through signoff to accelerate design convergence on TSMC A14 technology. In analog design, Synopsys is collaborating with TSMC on device routing enablement on A14, a key milestone for advanced analog place-and-route automation. Synopsys said its 3DIC Compiler platform now enables designers to co-design and simulate integrated voltage regulators on TSMC CoWoS technology in a unified environment, and that it continues to work with TSMC on co-packaged optics design on TSMC COUPE technology. On TSMC's N2P process, Synopsys achieved key IP enablement and tape-out milestones for AI and HPC designs including PCIe 7.0, HBM4, LPDDR6/5X/5, 224G Ethernet PHY, UCIe, OTP, and advanced SLM process, voltage, and temperature monitoring IP, and recently completed 64G UCIe IP tape-outs on both 2nm and 3nm process nodes.

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Synopsys announced expanded TSMC collaborations spanning A14 certification, agentic AI workflows, CoWoS 3DIC support, and N2P IP tape-out milestones.

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